1. Field of the Invention
This invention relates to NOR circuits in general and, more specifically, to a dynamic NOR decoder using current mode sensing techniques.
2. Brief Description of the Prior Art
Standard prior art dynamic NOR circuits are generally used in decoders or circuits with high fan-in NOR logic. This decode scheme has an advantage over its static NOR circuit counterpart because high fan-in can be obtained with good performance. However, there are two principal disadvantages present in prior art dynamic NOR circuitry. The first disadvantage is that these circuits display high power dissipation. This is due to the logic of the NOR function itself whereby all row decoders are charged and then all are discharged except the decoder for the one row being activated. This causes the decode (DEC) node for all decode lines not selected to be discharged to ground after having previously been charged prior to the selection being made. The decode (DEC) nodes can be highly capacitive, depending upon the size (fan-in) of the decoder circuit elements. This high node capacitance must be precharged by the power supply before the next cycle of operation, the precharging power consumption often being significant. The result of such node capacitance (stray capacitance) is excessive power drain as well as slowing of circuit operation. The second disadvantage is a race condition for which there must be compensation. A race exists between the enable decode (ENDEC) signal, which enables the decode portion of the circuit and the enable driver (ENDRV) signal, which enables the driver portion of the circuit. To insure correct operation, the ENDEC signal must become active some time earlier than the ENDRV signal because the ENDEC signal determines the signal upon which the driver circuit, controlled by the ENDRV signal, must operate. This critical timing insures that the signal at the DEC node is at the correct logic level before the row driver is enabled. If the proper timing is not met, a deselected row may glitch and provide an erroneous signal indicating selection thereof when, in fact, no such selection was made. Compensating for this race condition causes a delay in row access since the driver enabling time must be delayed to insure its operation subsequent to the decode enable operation, thereby causing the slowing down of the operation of the circuit.